The present invention is directed to methods and apparatus for generating precise timing information for use in signal processing applications, and more particularly to performing progressive block averaging on arbitrary input sample period values.
High precision timing information is generally provided to a signal processing or re-sampling circuitry using a phase-locked loop (PLL). The PLL may receive a feedback signal from a First-In-First-Out (FIFO) memory. The feedback signal may indicate to the PLL whether the read rate of the data from the FIFO (e.g., output sample rate) is too high or too low relative to the incoming sample rate. The PLL may then adjust the clock period accordingly to provide precise timing information. As defined herein precise timing information is the information (e.g., clock signals) that indicates the ideal conditions (e.g., clock rate) for processing incoming data signals. The FIFO circuit may be used to buffer the incoming data signal stream to allow the output of the FIFO to be read at an appropriate time.
A precise ratio between the input/output sample rates may be needed for further signal processing (e.g., re-sampling). For example, an audio/video signal processing circuit may be configured to processes data using a particular clock signal. However, the processing circuit may receive the data from a system which may use a different clock signal. Accordingly, a PLL albeit this difference, may help to provide the relative timing information. The signal quality of the processed (e.g., re-sampled) output may be directly proportional to the precision and accuracy of the timing information.
Although PLL devices can be used to generate precise clock information, they lack a simple implementation because they require complex multiplier circuits. Each stereo channel (in audio applications) may require its own PLL and may further increase the complexity of these designs.
The PLL designs may lack the ability to produce precise clock information quickly. This is because PLL designs may have a high start-up time (e.g., time to lock) when designed for low bandwidth applications and thus substantial time may be lost for the initial precise clock information generation. Further, the time to lock is non-deterministic and may vary on the condition of the input signal or data stream. Moreover, because PLL designs or similar feedback mechanisms oftentimes have a high start-up overhead they are limited in their ability to provide precise timing information for high number of bits of resolution (e.g., 20 or more).